China Job Listing

Company: ?????????????
Job Title: Senior Sr. Hardware Engineer
Job Description:
Company introduction: AAA is seeking a Software Engineer to design, implement, test and maintain real-time embedded software components in xDSL/POTS based line cards for the AAA C7 Platform.
Report To: Director of Engineering
Location: ??

Responsibilities:
1. As a member of the Design team, the qualified candidate will participate in all phases of hardware development cycle from concept through production of the next generation Telecom systems
2. The candidate will be responsible for
•Design and support of complex 10, and Digital circuitry.
•Board design which includes micro-processor and ASIC integration, schematic capture, part selection, and signal integrity analysis.
•Design Verification, and validation at board, and system level.
•Generating Engineering Requirements, Line Unit, and Integration Test plans.
•FPGA design, and simulation.

Requirements
1. Ability to conduct technical discussions, publish documents, and build knowledge base in English
2. Able to conduct technical discussion in English proficiently.
3. BSEE or MSEE
4. 5+ years of hardware design experience involved analog or digital design
5. 3+ years of experience with high-speed, high-density design
6. 3+ years of experience with schematic capture development and simulation tools
7. Able to travel to US for weeks if required
8. Excellent interpersonal, written and verbal communications skills
9. 2+ years experience working in projects that has HW/SW design and has gone through full project cycle from project initiation, design, implementation, integration, DVT, to GA.
10. Provide high quality deliverables, including documentations, software source code, and test results.
11. Quickly prioritize tasks and drive multiple tasks in parallel

DESIRED:
12. Demonstrated ability to contribute on an architectural level
13. Experience with telecom protocols, such as T1/E1, SONET/SDH, DS3, DSL
14. In-depth understanding of controlled impedance PCB design, clock distribution, and timing analysis
15. 2+ years of experience in FPGA design using Verilog or VHDL, simulation and synthesis tools, place and route tools, and static timing analysis.

* Please send us your complete resume (in Chinese and in English) to: 'topjob_it234@dacare.com'(Please replace "#" with "@")
* In the email subject please include the position name and job #